Search from the table of contents of 2.5 million books
Advanced Search (Beta)
Home > High Level Synthesis of ASICs under Timing and Synchronization Constraints

High Level Synthesis of ASICs under Timing and Synchronization Constraints


Book Informaton

High Level Synthesis of ASICs under Timing and Synchronization Constraints

Author

David C. Ku; Giovanni DeMicheli

Series

The Springer International Series in Engineering and Computer Science

Volume

177

Year of Publication

1992

Publisher

Springer US

City of Publication

Boston

Pages

XIV, 294

Language

en

ISBN

9780792392446, 9781475721171, 0792392442

ARI Id

1664873445583


Find on

World Cat

OpenLibrary

Internet Archive


This page has been accessed 5 times.
Access Options
Citation Options
Download Citation

Chapters/HeadingsAuthor(s)PagesInfo
Loading...
Chapters/HeadingsAuthor(s)PagesInfo