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Logic Synthesis and SOC Prototyping: RTL Design using VHDL


Book Informaton

Logic Synthesis and SOC Prototyping: RTL Design using VHDL

Author

Vaibbhav Taraate

Year of Publication

1st ed. 2020

Publisher

Springer Nature Singapore

Pages

XIX, 251

Language

EN

ISBN

9789811513138, 9789811513145, 9811513139

ARI Id

1665234672606


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