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Home > Field Programmable Logic and Application: 14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings > A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data
Field Programmable Logic and Application: 14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings |
Jürgen Becker; Marco Platzner; Serge Vernalde
Springer Berlin Heidelberg
Field Programmable Logic and Application: 14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings
A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data
Authors

Christophe Layer; Hans-Jörg Pfleiderer

ARI Id

1664217479558_800633

Access

Not Available Free

Pages

648-657

DOI

10.1007/978-3-540-30117-2_66

Chapter URL

https://rd.springer.com/chapter/10.1007/978-3-540-30117-2_66

Table of Contents of Book
Showing 1 to 20 of 179 entries
Chapters/HeadingsAuthor(s)PagesInfo
Front Matter
FPGAs and the Era of Field Programmability
Wim Roelandts
1-1
Reconfigurable Systems Emerge
Nick Tredennick; Brion Shimamoto
2-11
System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?
Mark Dickinson
12-12
Hardware Accelerated Novel Protein Identification
Anish Alex; Jonathan Rose; Ruth Isserlin-Weinberger; Christopher Hogue
13-22
Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices
Stefan Dydel; Piotr Bała
23-32
A Key Management Architecture for Securing Off-Chip Data Transfers
Jonathan Graf; Peter Athanas
33-42
FPGA Implementation of Biometric Authentication System Based on Hand Geometry
Celia López-Ongil; Raul Sanchez-Reillo; Judith Liu-Jimenez; Fernando Casado; Leslie Sánchez; Luis Entrena
43-53
SoftSONIC: A Customisable Modular Platform for Video Applications
Tero Rissa; Peter Y. K. Cheung; Wayne Luk
54-63
Deploying Hardware Platforms for SoC Validation: An Industrial Case Study
A. Bigot; F. Charpentier; H. Krupnova; I. Sans
64-73
Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes
Tim Kerins; Emanuel Popovici; William Marnane
74-83
Power Analysis Attacks Against FPGA Implementations of the DES
François-Xavier Standaert; Sıddıka Berna Örs; Jean-Jacques Quisquater; Bart Preneel
84-94
Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer
Maya Gokhale; Janette Frigo; Christine Ahrens; Justin L. Tripp; Ron Minnich
95-104
Stochastic Simulation for Biochemical Reactions on FPGA
M. Yoshimi; Y. Osana; T. Fukushima; H. Amano
105-114
Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures
Alexander Thomas; Juergen Becker
115-124
Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine
Frederick Furtek; Eugene Hogenauer; James Scheuermann
125-134
Improving FPGA Performance and Area Using an Adaptive Logic Module
Mike Hutton; Jay Schleicher; David Lewis; Bruce Pedersen; Richard Yuan; Sinan Kaptanoglu et al.
135-144
A Dual-V DD Low Power FPGA Architecture
A. Gayasen; K. Lee; N. Vijaykrishnan; M. Kandemir; M. J. Irwin; T. Tuan
145-157
Simultaneous Timing Driven Clustering and Placement for FPGAs
Gang Chen; Jason Cong
158-167
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
Jason Anderson; Sudip Nag; Kamal Chaudhary; Sandor Kalman; Chari Madabhushi; Paul Cheng
168-178
Chapters/HeadingsAuthor(s)PagesInfo
Showing 1 to 20 of 179 entries
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