Chapter: Test of Power Management Structures

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Home > Power-Aware Testing and Test Strategies for Low Power Devices > Test of Power Management Structures

Power-Aware Testing and Test Strategies for Low Power Devices |

Patrick Girard; Nicola Nicolici; Xiaoqing Wen

Springer US

Power-Aware Testing and Test Strategies for Low Power Devices

Test of Power Management Structures

Chapter Info

Authors

Mark Kassab; Mohammad Tehranipoor

ARI Id

1664222739323_821532

Access

Not Available Free

Pages

295-322

DOI

10.1007/978-1-4419-0928-2_10

Chapter URL

https://rd.springer.com/chapter/10.1007/978-1-4419-0928-2_10

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Chapters/Headings	Author(s)	Pages	Info
Front Matter		i-xxiii
Fundamentals of VLSI Testing	Laung-Terng Wang; Charles E. Stroud	1-29
Power Issues During Test	Sandip Kundu; Alodeep Sanyal	31-63
Low-Power Test Pattern Generation	Xiaoqing Wen; Seongmoon Wang	65-115
Power-Aware Design-for-Test	Hans-Joachim Wunderlich; Christian G. Zoellin	117-146
Power-Aware Test Data Compression and BIST	Sandeep Kumar Goel; Krishnendu Chakrabarty	147-173
Power-Aware System-Level Test Planning	Erik Larsson; C. P. Ravikumar	175-211
Low-Power Design Techniques and Test Implications	Kaushik Roy; Swarup Bhunia	213-242
Test Strategies for Multivoltage Designs	Saqib Khursheed; Bashir M. Al-Hashimi	243-271
Test Strategies for Gated Clock Designs	Brion Keller; Krishna Chakravadhanula	273-293
Test of Power Management Structures	Mark Kassab; Mohammad Tehranipoor	295-322
EDA Solution for Power-Aware Design-for-Test	Mokhtar Hirech	323-353
Back Matter		355-363
Chapters/Headings	Author(s)	Pages	Info

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