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Digital System Test and Testable Design: Using HDL Models and Architectures |
Springer US
Digital System Test and Testable Design: Using HDL Models and Architectures

Memory Testing by Means of Memory BIST
Authors

ARI Id

1664227065783_836932

Access

Not Available Free

Pages

375-391

DOI

10.1007/978-1-4419-7548-5_11

Chapter URL

https://rd.springer.com/chapter/10.1007/978-1-4419-7548-5_11

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