Search from the table of contents of 2.5 million books
Advanced Search (Beta)
Home > Parallel and Distributed Processing: 10th International IPPS/SPDP' 98 Workshops, Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30 - April 3, 1998, Proceedings > Building BSP programs using the refinement calculus
Parallel and Distributed Processing: 10th International IPPS/SPDP' 98 Workshops, Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30 - April 3, 1998, Proceedings |
Jose Rolim
Springer Berlin Heidelberg
Parallel and Distributed Processing: 10th International IPPS/SPDP' 98 Workshops, Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30 - April 3, 1998, Proceedings
Building BSP programs using the refinement calculus
Authors

D. B. Skillicorn

ARI Id

1664381509913_1444169

Access

Not Available Free

Pages

790-795

DOI

10.1007/3-540-64359-1_742

Chapter URL

https://rd.springer.com/chapter/10.1007/3-540-64359-1_742

Table of Contents of Book
Showing 1 to 20 of 120 entries
Chapters/HeadingsAuthor(s)PagesInfo
Front Matter
Dynamic reconfiguration of a PMMLA for high-throughput applications
Gautam Ghare; Soo-Young Lee
1-6
Virtual FPGAs: Some steps behind the physical barriers
William Fornaciari; Vincenzo Piuri
7-12
A parallel algorithm for minimum cost path computation on polymorphic processor array
P. Baglietto; M. Maersca; M. Migliardi
13-18
A performance modeling and analysis environment for reconfigurable computers
Jeffrey Walrath; Ranga Vemuri
19-24
Runtime reconfigurable routing
Gordon Brebner; Adam Donlin
25-30
An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures
Iyad Ouaiss; Sriram Govindarajan; Vinoo Srinivasan; Meenakshi Kaul; Ranga Vemuri
31-36
Temporal partitioning for partially-reconfigurable-field-programmable gate
John Spillane; Henry Owen
37-42
A Java development and runtime environment for reconfigurable computing
Don Davis; Michael Barr; Toby Bennett; Stephen Edwards; Jonathan Harris; Ian Miller et al.
43-48
Synthesizing reconfigurable sequential machines using Tabular models
Kamlesh Rath; Jian Li
49-54
Evaluation of a low-power reconfigurable DSP architecture
Arthur Abnous; Katsunori Seno; Yuji Ichikawa; Marlene Wan; Jan Rabaey
55-60
A reconfigurable hardware-monitor for communication analysis in distributed real-time systems
Andreas Kirschbaum; Jürgen Becker; Manfred Glesner
61-66
On reconfgurable co-processing units
Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann; Ulrich Nageldinger
67-72
A mathematical benefit analysis of context switching reconfigurable computing
Stephen M. Scalera; John J. Murray; Steve Lease
73-78
A configurable computing approach towards real-time target tracking
Bharadwaj Pudipeddi; A. Lynn Abbott; Peter M. Athanas
79-84
HOSMII: A virtual hardware integrated with DRAM
Yuichiro Shibata; Hidenori Miyazaki; Xiao-ping Ling; Hideharu Amano
85-90
Hardware reconfigurable neural networks
Jean-Luc Beuchat; Jacques-Olivier Haenni; Eduardo Sanchez
91-98
A simulator for the reconfigurable mesh architecture
Carsten Steckel; Martin Middendorf; Hossam ElGindy; Hartmut Schmeck
99-104
PACE: Processor architectures for circuit emulation
Reiner Kolla; Oliver Springauf
105-110
Multiparadigm, multilingual interoperability: Experience with converse
L. V. Kalé; Milind Bhandarkar; Robert Brunner; Joshua Yelon
111-122
Chapters/HeadingsAuthor(s)PagesInfo
Showing 1 to 20 of 120 entries
Similar Books
Similar Chapters
Similar Thesis

Similar News

Similar Articles
Similar Article Headings