Chapter: Layout of Digit-Serial Circuits

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Home > Digit-Serial Computation > Layout of Digit-Serial Circuits

Digit-Serial Computation |

Richard Hartley; Keshab K. Parhi

Springer US

Layout of Digit-Serial Circuits

Chapter Info

Authors

Richard Hartley; Keshab K. Parhi

ARI Id

1664541608492_2123115

Access

Not Available Free

Pages

95-106

DOI

10.1007/978-1-4615-2327-7_5

Chapter URL

https://rd.springer.com/chapter/10.1007/978-1-4615-2327-7_5

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Chapters/Headings	Author(s)	Pages	Info
Front Matter		i-xiii
Digit-Serial Architecture	Richard Hartley; Keshab K. Parhi	1-26
Digit-Serial Cell Design	Richard Hartley; Keshab K. Parhi	27-41
Multipliers	Richard Hartley; Keshab K. Parhi	43-61
Digit-Serial Input Language	Richard Hartley; Keshab K. Parhi	63-93
Layout of Digit-Serial Circuits	Richard Hartley; Keshab K. Parhi	95-106
Scheduling	Richard Hartley; Keshab K. Parhi	107-135
Digit-Serial Performance	Richard Hartley; Keshab K. Parhi	137-146
Bit-Level Unfolding	Richard Hartley; Keshab K. Parhi	147-163
The Folding Transformation	Richard Hartley; Keshab K. Parhi	165-182
Wavelet Transform Architectures	Richard Hartley; Keshab K. Parhi	183-194
Digit-Serial Systolic Arrays	Richard Hartley; Keshab K. Parhi	195-215
Canonic Signed Digit Arithmetic	Richard Hartley; Keshab K. Parhi	217-252
Online Arithmetic	Richard Hartley; Keshab K. Parhi	253-290
Back Matter		291-306
Chapters/Headings	Author(s)	Pages	Info

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