Home > Algorithms and Architectures for Parallel Processing: ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings > A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs
Algorithms and Architectures for Parallel Processing: ICA3PP 2016 Collocated Workshops: SCDT, TAPEMS, BigTrust, UCER, DLMCS, Granada, Spain, December 14-16, 2016, Proceedings |
Jesus Carretero; Javier Garcia-Blas; Victor Gergel; Vladimir Voevodin; Iosif Meyerov; Juan A. Rico-Gallego; Juan C. Díaz-Martín; Pedro Alonso; Juan Durillo; José Daniel Garcia Sánchez; Alexey L. Lastovetsky; Fabrizio Marozzo; Qin Liu; Zakirul Alam Bhuiyan; Karl Fürlinger; Josef Weidendorfer; José Gracia
Springer International Publishing
A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs
Chapter Info
ARI Id
1664701889557_2801161
Access
Not Available Free
Pages
174-188
DOI
Chapter URL
https://rd.springer.com/chapter/10.1007/978-3-319-49956-7_14
Table of Contents of Book
Showing 1 to 20 of 37 entries
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I-XXV | |||
1-1 | |||
3-17 | |||
18-29 | |||
30-42 | |||
43-61 | |||
62-75 | |||
76-90 | |||
91-104 | |||
105-105 | |||
107-114 | |||
115-124 | |||
125-135 | |||
136-145 | |||
146-155 | |||
157-157 | |||
159-173 | |||
174-188 | |||
189-189 | |||
191-200 | |||
Chapters/Headings | Author(s) | Pages | Info |
Showing 1 to 20 of 37 entries
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