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Home > Transactions on High-Performance Embedded Architectures and Compilers IV > Compiler Directed Issue Queue Energy Reduction
Transactions on High-Performance Embedded Architectures and Compilers IV |
Per Stenström
Springer Berlin Heidelberg
Transactions on High-Performance Embedded Architectures and Compilers IV
Compiler Directed Issue Queue Energy Reduction
Authors

Timothy M. Jones; Michael F. P. O’Boyle; Jaume Abella; Antonio González

ARI Id

1664706561071_2829355

Access

Not Available Free

Pages

42-62

DOI

10.1007/978-3-642-24568-8_3

Chapter URL

https://rd.springer.com/chapter/10.1007/978-3-642-24568-8_3

Table of Contents of Book
Showing 1 to 20 of 23 entries
Chapters/HeadingsAuthor(s)PagesInfo
Front Matter
A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors
Magnus Jahre; Lasse Natvig
1-20
Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces
Frederik Vandeputte; Lieven Eeckhout
21-41
Compiler Directed Issue Queue Energy Reduction
Timothy M. Jones; Michael F. P. O’Boyle; Jaume Abella; Antonio González
42-62
A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors
Ben Cope; Peter Y. K. Cheung; Wayne Luk; Lee Howes
63-83
Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors
Omer Khan; Sandip Kundu
84-110
A Highly Scalable Parallel Implementation of H. 264
Arnaldo Azevedo; Ben Juurlink; Cor Meenderinck; Andrei Terechko; Jan Hoogerbrugge; Mauricio Alvarez et al.
111-134
Communication Based Proactive Link Power Management
Sai Prashanth Muralidhara; Mahmut Kandemir
135-154
Finding Extreme Behaviors in Microprocessor Workloads
Frederik Vandeputte; Lieven Eeckhout
155-174
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
Michael B. Henry; Leyla Nazhandali
175-194
Transaction Reordering to Reduce Aborts in Software Transactional Memory
Mohammad Ansari; Mikel Luján; Christos Kotselidis; Kim Jarvis; Chris Kirkham; Ian Watson
195-214
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture
Yasutaka Wada; Akihiro Hayashi; Takeshi Masuura; Jun Shirako; Hirofumi Nakano; Hiroaki Shikano et al.
215-233
A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM
Xiongfei Liao; Wu Jigang; Thambipillai Srikanthan
234-253
Software Transactional Memory Validation – Time and Space Considerations
Adam Welc; Bratin Saha
254-273
Tiled Multi-Core Stream Architecture
Nan Wu; Qianming Yang; Mei Wen; Yi He; Ju Ren; Maolin Guan et al.
274-293
An Efficient and Flexible Task Management for Many Cores
Yuan Nan; Yu Lei; Fan Dong-rui
294-310
On Two-Layer Brain-Inspired Hierarchical Topologies – A Rent’s Rule Approach –
Valeriu Beiu; Basheer A. M. Madappuram; Peter M. Kelly; Liam J. McDaid
311-333
Advanced Packet Segmentation and Buffering Algorithms in Network Processors
Daniel Llorente; Kimon Karras; Thomas Wild; Andreas Herkersdorf
334-353
Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation
W. G. Osborne; W. Luk; J. G. F. Coutinho; O. Mencer
354-369
A Cost Model for Partial Dynamic Reconfiguration
Markus Rullmann; Renate Merker
370-390
Chapters/HeadingsAuthor(s)PagesInfo
Showing 1 to 20 of 23 entries
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