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Home > Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers > Subthreshold Circuit Design for Ultra-Low-Power Applications
Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers |
José Monteiro; Rene van Leuken
Springer Berlin Heidelberg
Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers
Subthreshold Circuit Design for Ultra-Low-Power Applications
Authors

Yusuf Leblebici

ARI Id

1664773498990_3160935

Access

Not Available Free

Pages

3-3

DOI

10.1007/978-3-642-11802-9_3

Chapter URL

https://rd.springer.com/chapter/10.1007/978-3-642-11802-9_3

Table of Contents of Book
Showing 1 to 20 of 42 entries
Chapters/HeadingsAuthor(s)PagesInfo
Front Matter
Robust Low Power Embedded SRAM Design: From System to Memory Cell
Toby Doorn; Roelof Salters
1-1
Variability in Advanced Nanometer Technologies: Challenges and Solutions
Davide Pandini
2-2
Subthreshold Circuit Design for Ultra-Low-Power Applications
Yusuf Leblebici
3-3
SystemC AMS Extensions: New Language – New Methods – New Applications
Martin Barnasconi; Markus Damm; Karsten Einwich
4-4
Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation
Mohsen Raji; Behnam Ghavami; Hamid R. Zarandi; Hossein Pedram
5-15
Interpreting SSTA Results with Correlation
Zeqin Wu; Philippe Maurine; Nadine Azemard; Gille Ducharme
16-25
Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units
Ioannis Kouretas; Vassilis Paliouras
26-35
Exponent Monte Carlo for Quick Statistical Circuit Simulation
Paul Zuber; Vladimir Matvejev; Philippe Roussel; Petr Dobrovolný; Miguel Miranda
36-45
Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis
Monica Figueiredo; Rui L. Aguiar
46-55
A Hardware Implementation of the User-Centric Display Energy Management
Vasily G. Moshnyaga; Koji Hashimoto; Tadashi Suetsugu; Shuhei Higashi
56-65
On-chip Thermal Modeling Based on SPICE Simulation
Wei Liu; Andrea Calimera; Alberto Nannarelli; Enrico Macii; Massimo Poncino
66-75
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures
Javier Castro; Pilar Parra; Antonio J. Acosta
76-85
Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip
Iraklis Anagnostopoulos; Alexandros Bartzas; Dimitrios Soudris
86-95
Data-Driven Clock Gating for Digital Filters
Alberto Bonanno; Alberto Bocca; Alberto Macii; Enrico Macii; Massimo Poncino
96-105
Power Management and Its Impact on Power Supply Noise
Howard Chen; Indira Nair
106-115
Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems
Muhammad Khurram Bhatti; Muhammad Farooq; Cécile Belleudy; Michel Auguin; Ons Mbarek
116-126
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0. 5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique
Chih-Hsiang Lin; James B. Kuo
127-135
Crosstalk in High-Performance Asynchronous Designs
Ritej Bachhawat; Pankaj Golani; Peter A. Beerel
136-145
Modeling and Reducing EMI in GALS and Synchronous Systems
Tomasz Król; Milos Krstić; Xin Fan; Eckhard Grass
146-155
Chapters/HeadingsAuthor(s)PagesInfo
Showing 1 to 20 of 42 entries
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