Chapter: Variation-Tolerant Microprocessor Architecture at Low Power

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Home > Low-Power Variation-Tolerant Design in Nanometer Silicon > Variation-Tolerant Microprocessor Architecture at Low Power

Low-Power Variation-Tolerant Design in Nanometer Silicon |

Swarup Bhunia; Saibal Mukhopadhyay

Springer US

Low-Power Variation-Tolerant Design in Nanometer Silicon

Variation-Tolerant Microprocessor Architecture at Low Power

Chapter Info

Authors

Meeta S. Gupta; Pradip Bose

ARI Id

1664823863147_3666486

Access

Not Available Free

Pages

211-247

DOI

10.1007/978-1-4419-7418-1_7

Chapter URL

https://rd.springer.com/chapter/10.1007/978-1-4419-7418-1_7

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