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Home > Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers > A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers |
Lars Svensson; José Monteiro
Springer Berlin Heidelberg
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers
A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption
Authors

Gustavo Callou; Paulo Maciel; Ermeson Carneiro; Bruno Nogueira; Eduardo Tavares; Meuse Oliveira Jr.

ARI Id

1664839403001_3731315

Access

Not Available Free

Pages

379-388

DOI

10.1007/978-3-540-95948-9_38

Chapter URL

https://rd.springer.com/chapter/10.1007/978-3-540-95948-9_38

Table of Contents of Book
Showing 1 to 20 of 50 entries
Chapters/HeadingsAuthor(s)PagesInfo
Front Matter
Subthreshold FIR Filter Architecture for Ultra Low Power Applications
Biswajit Mishra; Bashir M. Al-Hashimi
1-10
Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs
Bahman Kheradmand Boroujeni; Christian Piguet; Yusuf Leblebici
11-20
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits
Armin Tajalli; Massimo Alioto; Elizabeth J. Brauer; Yusuf Leblebici
21-30
Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction
Matteo Agostinelli; Massimo Alioto; David Esseni; Luca Selmi
31-41
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating
Ashoka Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino
42-51
Intelligate: Scalable Dynamic Invariant Learning for Power Reduction
Roni Wiener; Gila Kamhi; Moshe Y. Vardi
52-61
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
Masanori Muroyama; Tohru Ishihara; Hiroto Yasuura
62-71
Power-Aware Design via Micro-architectural Link to Implementation
Yoni Aizik; Gila Kamhi; Yael Zbar; Hadas Ronen; Muhammad Abozaed
72-81
Untraditional Approach to Computer Energy Reduction
Vasily G. Moshnyaga
82-92
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication
Ioannis Kouretas; Vassilis Paliouras
93-102
Power Optimization of Parallel Multipliers in Systems with Variable Word-Length
Saeeid Tahmasbi Oskuii; Per Gunnar Kjeldsberg; Lars Lundheim; Asghar Havashki
103-115
A Design Space Comparison of 6T and 8T SRAM Core-Cells
Florian Bauer; Georg Georgakos; Doris Schmitt-Landsiedel
116-125
Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization
Yan Li; Helmut Schneider; Florian Schnabel; Roland Thewes; Doris Schmitt-Landsiedel
126-135
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic
Massimo Alioto; Gaetano Palumbo; Melita Pennisi
136-145
A Study on CMOS Time Uncertainty with Technology Scaling
Monica Figueiredo; Rui L. Aguiar
146-155
Static Timing Model Extraction for Combinational Circuits
Bing Li; Christoph Knoth; Walter Schneider; Manuel Schmidt; Ulf Schlichtmann
156-166
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
Walter Schneider; Manuel Schmidt; Bing Li; Ulf Schlichtmann
167-177
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power
Howard Chen; Scott Neely; Jinjun Xiong; Vladimir Zolotov; Chandu Visweswariah
178-187
Logic Synthesis of Handshake Components Using Structural Clustering Techniques
Francisco Fernández-Nogueira; Josep Carmona
188-198
Chapters/HeadingsAuthor(s)PagesInfo
Showing 1 to 20 of 50 entries
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