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Home > Artificial Neural Nets. Problem Solving Methods: 7th International Work-Conference on Artificial and Natural Neural Networks, IWANN 2003, Maó, Menorca, Spain, June 3-6. Proceedings, Part II > The Knowledge Engineering approach to Autonomous Robotics
Artificial Neural Nets. Problem Solving Methods: 7th International Work-Conference on Artificial and Natural Neural Networks, IWANN 2003, Maó, Menorca, Spain, June 3-6. Proceedings, Part II |
José Mira; José R. Alvarez
Springer Berlin Heidelberg
Artificial Neural Nets. Problem Solving Methods: 7th International Work-Conference on Artificial and Natural Neural Networks, IWANN 2003, Maó, Menorca, Spain, June 3-6. Proceedings, Part II
The Knowledge Engineering approach to Autonomous Robotics
Authors

Jose Mira; José Ramón; Álvarez Sánchez; Félix de la Paz Lopez

ARI Id

1664970451222_4282691

Access

Not Available Free

Pages

161-168

DOI

10.1007/3-540-44869-1_21

Chapter URL

https://rd.springer.com/chapter/10.1007/3-540-44869-1_21

Table of Contents of Book
Showing 1 to 20 of 104 entries
Chapters/HeadingsAuthor(s)PagesInfo
Front Matter
I-XXVII
FPGA Implementation of a Perceptron-like Neural Network for Embedded Applications
Eva M. Ortigosa; Antonio Cañas; Eduardo Ros; Richard R. Carrillo
1-8
NSP: a Neuro–Symbolic Processor
Ernesto Burattini; Massimo De Gregorio; Victor M. G. Ferreira; Felipe M. G. França
9-16
Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron
Nadia Nedjah; Luiza de Macedo Mourelle
17-24
Current mode CMOS synthesis of a motor–control neural system
Ginés Doménech-Asensi; Ramón Ruiz-Merino; Hans Hauer; José Ángel Díaz-Madrid
25-32
New emulated discrete model of CNN architecture for FPGA and DSP applications
Martínez J.J.; Toledo F.J.; Ferrández J.M.
33-40
A Binary Multiplier Using RTD Based Threshold Logic Gates
P M Kelly; C J Thompson; T M McGinnity; L P Maguire
41-48
Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL)
Suryanarayana Tatapudi; Valeriu Beiu
49-56
UV-programmable Floating-Gate CMOS Linear Threshold Element ”P1N3”
Snorre Aunet; Yngvar Berg
57-64
CMOS Implementation of Generalized Threshold Functions
Marius Padure; Sorin Cotofana; Stamatis Vassiliadis
65-72
A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder
Peter Celinski; Sorin D. Cotofana; Derek Abbott
73-80
Validation of a Cortical Electrode Model for Neuroprosthetics purposes
García-de-Quirós F.J; Bonomini M.P.; Ferrández J.M.; Fernández E.
81-88
XMLP: a Feed-Forward Neural Network with Two-Dimensional Layers and Partial Connectivity
Antonio Canas; Eva M. Ortigosa; Antonio F. Díaz; Julio Ortega
89-96
An analogue current–mode hardware design proposal for preprocessing layers in ART-based neural networks
José-Alejandro López Alcantud; José-Ángel Díaz Madrid; Hans Hauer; Ramón Ruiz Merino
97-104
On the effects of dimensionality on data analysis with neural networks
M. Verleysen; D. Francois; G. Simon; V. Wertz
105-112
Hardware Optimization of a Novel Spiking Neuron Model for the POEtic tissue.
Oriol Torres; Jan Eriksson; Juan Manuel Moreno; Alessandro Villa
113-120
Implementing a Margolus Neighborhood Cellular Automata on a FPGA
Joaquín Cerda; Rafael Gadea; Guillermo Paya
121-128
An Empirical Comparison of Training Algorithms for Radial Basis Functions
Mamen Ortiz-Gómez; Carlos Hernández-Espinosa; Mercedes Fernández-Redondo
129-136
Ensemble Methods for Multilayer Feedforward: An Experimental Study
Carlos Hernández-Espinosa; Mercedes Fernández-Redondo; Mamen Ortiz-Gómez
137-144
Post-synaptic Time-dependent Conductances in Spiking Neurons: FPGA Implementation of a Flexible Cell Model
Eduardo Ros; Rodrigo Agis; Richard R. Carrillo; Eva M. Ortigosa
145-152
Chapters/HeadingsAuthor(s)PagesInfo
Showing 1 to 20 of 104 entries
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