Chapter: Exploring the Platform for Expressing SystemVerilog Assertions in Model Based System Engineering

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Home > Information Science and Applications (ICISA) 2016 > Exploring the Platform for Expressing SystemVerilog Assertions in Model Based System Engineering

Information Science and Applications (ICISA) 2016 |

Kuinam J. Kim; Nikolai Joukov

Springer Nature Singapore

Information Science and Applications (ICISA) 2016

Exploring the Platform for Expressing SystemVerilog Assertions in Model Based System Engineering

Chapter Info

Authors

Muhammad Rashid; Muhammad Waseem Anwar; Farooque Azam; Muhammad Kashif

ARI Id

1665030200911_4537316

Access

Not Available Free

Pages

533-544

DOI

10.1007/978-981-10-0557-2_53

Chapter URL

https://rd.springer.com/chapter/10.1007/978-981-10-0557-2_53

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