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Home > Applied Reconfigurable Computing. Architectures, Tools, and Applications: 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings > DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability
Applied Reconfigurable Computing. Architectures, Tools, and Applications: 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings |
Nikolaos Voros; Michael Huebner; Georgios Keramidas; Diana Goehringer; Christos Antonopoulos; Pedro C. Diniz
Springer International Publishing
Applied Reconfigurable Computing. Architectures, Tools, and Applications: 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings
DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability
Authors

Jeckson Dellagostin Souza; Anderson L. Sartor; Luigi Carro; Mateus Beck Rutzig; Stephan Wong; Antonio C. S. Beck

ARI Id

1665115957036_4896657

Access

Not Available Free

Pages

367-378

DOI

10.1007/978-3-319-78890-6_30

Chapter URL

https://rd.springer.com/chapter/10.1007/978-3-319-78890-6_30

Table of Contents of Book
Showing 1 to 20 of 70 entries
Chapters/HeadingsAuthor(s)PagesInfo
Front Matter
I-XVI
Front Matter
1-1
Approximate FPGA-Based LSTMs Under Computation Time Constraints
Michalis Rizakis; Stylianos I. Venieris; Alexandros Kouris; Christos-Savvas Bouganis
3-15
Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification
Jiang Su; Julian Faraone; Junyi Liu; Yiren Zhao; David B. Thomas; Philip H. W. Leong et al.
16-28
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic
Jiang Su; Nicholas J. Fraser; Giulio Gambardella; Michaela Blott; Gianluca Durelli; David B. Thomas et al.
29-42
Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud
Kazusa Musha; Tomohiro Kudoh; Hideharu Amano
43-54
SqueezeJet: High-Level Synthesis Accelerator Design for Deep Convolutional Neural Networks
Panagiotis G. Mousouliotis; Loukas P. Petrou
55-66
Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering
Konstantinos Katsantonis; Christoforos Kachris; Dimitrios Soudris
67-78
Front Matter
79-79
VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express
Oğuzhan Sezenlik; Sebastian Schüller; Joachim K. Anlauf
81-92
Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling
Lukas Johannes Jung; Christian Hochberger
93-104
Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network
Kalindu Herath; Alok Prakash; Thambipillai Srikanthan
105-118
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design
Farhad Merchant; Tarun Vatwani; Anupam Chattopadhyay; Soumyendu Raha; S. K. Nandy; Ranjani Narayan
119-131
FPGA-Based Memory Efficient Shift-And Algorithm for Regular Expression Matching
Junsik Kim; Jaehyun Park
132-141
Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study
Kazuei Hironaka; Ng. Anh Vu Doan; Hideharu Amano
142-150
Front Matter
151-151
An FPGA/HMC-Based Accelerator for Resolution Proof Checking
Tim Hansmeier; Marco Platzner; David Andrews
153-165
An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm
Almabrok Abdoalnasir; Mihalis Psarakis; Anastasios Dounis
166-177
ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs
Santhi Natarajan; N. KrishnaKumar; Debnath Pal; S. K. Nandy
178-191
FPGA-Based Parallel Pattern Matching
Masahiro Fukuda; Yasushi Inoguchi
192-203
Chapters/HeadingsAuthor(s)PagesInfo
Showing 1 to 20 of 70 entries
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