Chapter: Processor Cores and Architecture Design

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Home > Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog > Processor Cores and Architecture Design

Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog |

Vaibbhav Taraate

Springer Nature Singapore

Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog

Processor Cores and Architecture Design

Chapter Info

Authors

Vaibbhav Taraate

ARI Id

1665160300721_5094760

Access

Not Available Free

Pages

63-95

DOI

10.1007/978-981-10-8776-9_5

Chapter URL

https://rd.springer.com/chapter/10.1007/978-981-10-8776-9_5

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Chapters/Headings	Author(s)	Pages	Info
Front Matter		i-xxi
Introduction	Vaibbhav Taraate	1-16
SOC Design	Vaibbhav Taraate	17-24
RTL Design Guidelines	Vaibbhav Taraate	25-50
RTL Design and Verification	Vaibbhav Taraate	51-62
Processor Cores and Architecture Design	Vaibbhav Taraate	63-95
Buses and Protocols in SOC Designs	Vaibbhav Taraate	97-117
Memory and Memory Controllers	Vaibbhav Taraate	119-139
DSP Algorithms and Video Processing	Vaibbhav Taraate	141-158
ASIC and FPGA Synthesis	Vaibbhav Taraate	159-172
Static Timing Analysis	Vaibbhav Taraate	173-196
SOC Prototyping	Vaibbhav Taraate	197-210
SOC Prototyping Guidelines	Vaibbhav Taraate	211-230
Design Integration and SOC Synthesis	Vaibbhav Taraate	231-245
Interconnect Delays and Timing	Vaibbhav Taraate	247-262
SOC Prototyping and Debug Techniques	Vaibbhav Taraate	263-276
Testing at the Board Level	Vaibbhav Taraate	277-290
Back Matter		291-307
Chapters/Headings	Author(s)	Pages	Info

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