Chapter: Low-Power Technique for 3D Interconnects

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Home > 3D Interconnect Architectures for Heterogeneous Technologies: Modeling and Optimization > Low-Power Technique for 3D Interconnects

3D Interconnect Architectures for Heterogeneous Technologies: Modeling and Optimization |

Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck

Springer International Publishing

3D Interconnect Architectures for Heterogeneous Technologies: Modeling and Optimization

Low-Power Technique for 3D Interconnects

Chapter Info

Authors

Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck

ARI Id

1665394968735_6239866

Access

Not Available Free

Pages

155-176

DOI

10.1007/978-3-030-98229-4_8

Chapter URL

https://rd.springer.com/chapter/10.1007/978-3-030-98229-4_8

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Chapters/Headings	Author(s)	Pages	Info
Front Matter		i-xxv
Front Matter		1-1
Introduction to 3D Technologies	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	3-25
Interconnect Architectures for 3D Technologies	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	27-47
Front Matter		49-49
High-Level Formulas for the 3D-Interconnect Power Consumption and Performance	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	51-70
High-Level Estimation of the 3D-Interconnect Capacitances	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	71-100
Front Matter		101-101
Models for Application Traffic and 3D-NoC Simulation	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	103-112
Estimation of the Bit-Level Statistics	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	113-132
Ratatoskr: A Simulator for NoCs in Heterogeneous 3D SoCs	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	133-151
Front Matter		153-153
Low-Power Technique for 3D Interconnects	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	155-176
Low-Power Technique for High-Performance 3D Interconnects	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	177-202
Low-Power Technique for High-Performance 3D Interconnects in the Presence of Temporal Misalignment	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	203-226
Low-Power Technique for Yield-Enhanced 3D Interconnects	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	227-263
Front Matter		265-265
Heterogeneous Buffering for 3D NoCs	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	267-280
Heterogeneous Routing for 3D NoCs	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	281-311
Heterogeneous Virtualisation for 3D NoCs	Lennart Bamberg; Jan Moritz Joseph; Alberto García-Ortiz; Thilo Pionteck	313-322
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