Chapter: System/Network-On-Chip Test Architectures

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Home > System-on-Chip Test Architectures > System/Network-On-Chip Test Architectures

System-on-Chip Test Architectures |

Laung-Terng Wang; Charles E. Stroud and Nur A. Touba

Morgan Kaufmann

System/Network-On-Chip Test Architectures

Chapter Info

Authors

Chunsheng Liu; Krishnendu Chakrabarty; Wen-Ben Jone

ARI Id

1665578117363_17336601

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Not Available Free

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Chapters/Headings	Author(s)	Pages	Info
Introduction	Laung-Terng (L.-T.) Wang; Charles E. Stroud; Nur A. Touba
Digital Test Architectures	Laung-Terng (L.-T.) Wang
Fault-Tolerant Design	Nur A. Touba
System/Network-On-Chip Test Architectures	Chunsheng Liu; Krishnendu Chakrabarty; Wen-Ben Jone
SIP Test Architectures	Philippe Cauvet; Michel Renovell; Serge Bernard
Delay Testing	Duncan M. (Hank) Walker; Michael S. Hsiao
Low-Power Testing	Patrick Girard; Xiaoqing Wen; Nur A. Touba
Coping with Physical Failures, Soft Errors, and Reliability Issues	Laung-Terng (L.-T.) Wang; Mehrdad Nourani; T.M. Mak
Design for Manufacturability and Yield	Robert C. Aitken
Design for Debug and Diagnosis	T.M. Mak; Srikanth Venkataraman
Software-Based Self-Testing	Jiun-Lang Huang; Kwang-Ting (Tim)
Field Programmable Gate Array Testing	Charles E. Stroud
MEMS Testing	Ramesh Ramadoss; Robert Dean; Xingguo Xiong
High-Speed I/O Interfaces	Mike Peng Li; T.M. Mak; Kwang-Ting (Tim) Cheng
Analog and Mixed-Signal Test Architectures	F. Foster Dai; Charles E. Stroud
RF Testing	Soumendu Bhattacharya; Abhijit Chatterjee
Testing Aspects of Nanotechnology Trends	Mehdi B. Tahoori; Niraj K. Jha; R. Iris Bahar
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