Chapter: Design of Component-Level On-Chip ESD Protection for Integrated Circuits

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Home > Electrostatic Discharge Protection: Advances and Applications > Design of Component-Level On-Chip ESD Protection for Integrated Circuits

Electrostatic Discharge Protection: Advances and Applications |

Juin J. Liou

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Electrostatic Discharge Protection: Advances and Applications

Design of Component-Level On-Chip ESD Protection for Integrated Circuits

Chapter Info

Authors

Charvaka Duvvury

ARI Id

1666057850680_14590081

Access

Not Available Free

Pages

13-30

DOI

10.1201/b18976-2

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Chapters/Headings	Author(s)	Pages	Info
Introduction to Electrostatic Discharge Protection	Juin J. Liou	1-12
Design of Component-Level On-Chip ESD Protection for Integrated Circuits	Charvaka Duvvury	13-30
ESD and EOS: Failure Mechanisms and Reliability	Nathaniel Peachey; Kevin Mello	31-50
ESD, EOS, and Latch-Up Test Methods and Associated Reliability Concerns	Alan W. Righter	51-66
Design of Power-Rail ESD Clamp Circuits with Gate-Leakage Consideration in Nanoscale CMOS Technology	Ming-Dou Ker; Chih-Ting Yeh	67-86
ESD Protection in Automotive Integrated Circuit Applications	Javier A. Salcedo; Jean-Jacques Hajjar	87-112
ESD Sensitivity of GaN-Based Electronic Devices	Gaudenzio Meneghesso; Matteo Meneghini; Enrico Zanoni	113-140
ESD Protection Circuits Using NMOS Parasitic Bipolar Transistor	Teruo Suzuki	141-162
ESD Development in Foundry Processes	Jim Vinson	163-184
Compact Modeling of Semiconductor Devices for Electrostatic Discharge Protection Applications	Zhenghao Gan; Waisum Wong	185-212
Advanced TCAD Methods for System-Level ESD Design	Vladislav A. Vashchenko; Andrei A. Shibkov	213-250
ESD Protection of Failsafe and Voltage-Tolerant Signal Pins	David L. Catlett Jr; Roger A. Cline; Ponnarith Pok	251-268
ESD Design and Optimization in Advanced CMOS SOI Technology	You Li	269-294
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