Chapter: Architecture Design of Network-on-Chip

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Home > Network-on-Chip: The Next Generation of System-on-Chip Integration > Architecture Design of Network-on-Chip

Network-on-Chip: The Next Generation of System-on-Chip Integration |

Santanu Kundu; Santanu Chattopadhyay

Routledge

Network-on-Chip: The Next Generation of System-on-Chip Integration

Architecture Design of Network-on-Chip

Chapter Info

Authors

Santanu Kundu; Santanu Chattopadhyay

ARI Id

1666063989044_14609257

Access

Open/Free Access

Pages

53-74

DOI

10.1201/9781315216072-3

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Chapters/Headings	Author(s)	Pages	Info
Introduction	Santanu Kundu; Santanu Chattopadhyay	1-12
Interconnection Networks in Network-on-Chip	Santanu Kundu; Santanu Chattopadhyay	13-51
Architecture Design of Network-on-Chip	Santanu Kundu; Santanu Chattopadhyay	53-74
Evaluation of Network-on-Chip Architectures	Santanu Kundu; Santanu Chattopadhyay	75-118
Application Mapping on Network-on-Chip	Santanu Kundu; Santanu Chattopadhyay	119-154
Low-Power Techniques for Network-on-Chip	Santanu Kundu; Santanu Chattopadhyay	155-190
Signal Integrity and Reliability of Network-on-Chip	Santanu Kundu; Santanu Chattopadhyay	191-234
Testing of Network-on-Chip Architectures	Santanu Kundu; Santanu Chattopadhyay	235-261
Application-Specific Network-on-Chip Synthesis	Santanu Kundu; Santanu Chattopadhyay	263-287
Reconfigurable Network-on-Chip Design	Santanu Kundu; Santanu Chattopadhyay	289-315
Three-Dimensional Integration of Network-on-Chip	Santanu Kundu; Santanu Chattopadhyay	317-352
Conclusions and Future Trends	Santanu Kundu; Santanu Chattopadhyay	353-357
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