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Home > Field-Programmable Logic and Applications: 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings > Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing
Field-Programmable Logic and Applications: 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings |
Gordon Brebner; Roger Woods
Springer Berlin Heidelberg
Field-Programmable Logic and Applications: 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings
Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing
Authors

Abbes Amira; Ahmed Bouridane; Peter Milligan

ARI Id

1674219756474_3332432

Access

Not Available Free

Pages

101-111

DOI

10.1007/3-540-44687-7_11

Chapter URL

https://rd.springer.com/chapter/10.1007/3-540-44687-7_11

Table of Contents of Book
Showing 1 to 20 of 76 entries
Chapters/HeadingsAuthor(s)PagesInfo
Front Matter
I-XV
Technology Trends and Adaptive Computing
Michael J. Flynn; Albert A. Liddicoat
1-5
Prototyping Framework for Reconfigurable Processors
Sergej Sawitzki; Steffen Köhler; Rainer G. Spallek
6-16
An Emulator for Exploring RaPiD Configurable Computing Architectures
Chris Fisher; Kevin Rennie; Guanbin Xing; Stefan G. Berg; Kevin Bolding; John Naegle et al.
17-26
A New Placement Method for Direct Mapping into LUT-Based FPGAs
Joerg Abke; Erich Barke
27-36
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits
Parivallal Kannan; Shankar Balachandran; Dinesh Bhatia
37-47
Macrocell Architectures for Product Term Embedded Memory Arrays
Ernie Lin; Steven J. E. Wilton
48-58
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs
Bryan S. Goda; Kraft Russell P.; Steven R. Carlough; Thomas W. Krawczyk Jr.; John F. McDonald
59-69
Memory Synthesis for FPGA-Based Reconfigurable Computers
Amit Kasat; Iyad Ouaiss; Ranga Vemuri
70-80
Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic
Stephen J. Melnikoff; Steven F. Quigley; Martin J. Russell
81-90
Implementation of (Normalised) RLS Lattice on Virtex
Felix Albu; Jiri Kadlec; Chris Softley; Rudolf Matousek; Antonin Hermanek; Nick Coleman et al.
91-100
Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing
Abbes Amira; Ahmed Bouridane; Peter Milligan
101-111
Static Profile-Driven Compilation for FPGAs
Srihari Cadambi; Seth Copen Goldstein
112-122
Synthesizing RTL Hardware from Java Byte Codes
Michael J. Wirthlin; Brad L. Hutchings; Carl Worth
123-132
PuMA++: From Behavioral Specification to Multi-FPGA-Prototype
Klaus Harbich; Erich Barke
133-141
Secure Configuration of Field Programmable Gate Arrays
Tom Kean
142-151
Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm
Máire McLoone; John V. McCanny
152-161
JBits™ Implementations of the Advanced Encryption Standard (Rijndael)
Scott McMillan; Cameron Patterson
162-171
Task-Parallel Programming of Reconfigurable Systems
Markus Weinhardt; Wayne Luk
172-181
Chip-Based Reconfigurable Task Management
Gordon Brebner; Oliver Diessel
182-191
Chapters/HeadingsAuthor(s)PagesInfo
Showing 1 to 20 of 76 entries
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