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Home > VLSI Design and Test: 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Proceedings > Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application
VLSI Design and Test: 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Proceedings |
Manoj Singh Gaur; Mark Zwolinski; Vijay Laxmi; Dharmendra Boolchandani; Virendra Sing; Adit D. Sing
Springer Berlin Heidelberg
VLSI Design and Test: 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Proceedings
Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application
Authors

Amit Sharma; Ravindra Mukhiya; S. Santosh Kumar; B. D. Pant

ARI Id

1674219842092_3475982

Access

Not Available Free

Pages

94-99

DOI

10.1007/978-3-642-42024-5_12

Chapter URL

https://rd.springer.com/chapter/10.1007/978-3-642-42024-5_12

Table of Contents of Book
Showing 1 to 20 of 46 entries
Chapters/HeadingsAuthor(s)PagesInfo
Front Matter
Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM
Bhupendra Singh Reniwal; Santosh Kumar Vishvakarma
1-9
A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator
Gudlavalleti Rajahari; Yashu Anand Varshney; Subash Chandra Bose
10-18
A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier
Vivek Verma; Chetan D. Parikh
19-25
An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network
R. K. Naga Mahesh; Akash Ganesan; Manchi Pavan Kumar; Roy Paily
26-34
Computational Functions’ VLSI Implementation for Compressed Sensing
Shrirang Korde; Amol Khandare; Raghavendra Deshmukh; Rajendra Patrikar
35-43
A Novel Input Capacitance Modeling Methodology for Nano-Scale VLSI Standard Cell Library Characterization
Akhtar W. Alam; Esakkimuthu Dhakshinamoorthy; Prince Mathew; Narender Ponna
44-48
An Area Efficient Wide Range On-Chip Delay Measurement Architecture
Rahul Krishnamurthy; G. K. Sharma
49-58
10 Gbps Current Mode Logic I/O Buffer
Akhil Rathore; Chetan D Parikh
59-65
Kapees: A New Tool for Standard Cell Placement
Sameer Pawanekar; Kalpesh Kapoor; Gaurav Trivedi
66-73
Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization
Kanchan Manna; Shailesh Singh; Santanu Chattopadhyay; Indranil Sengupta
74-82
Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence
Sumanta Pyne; Ajit Pal
83-93
Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application
Amit Sharma; Ravindra Mukhiya; S. Santosh Kumar; B. D. Pant
94-99
Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology
Himadri Singh Raghav; Sachin Maheshwari; B. Prasad Singh
100-107
Characterization of Logical Effort for Improved Delay
Sachin Maheshwari; Himadri Singh Raghav; Anu Gupta
108-117
A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance
Ratul Kumar Baruah; Roy P. Paily
118-127
An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design
Somnath Paul; Abhijit Dana; Soumya Pandit
128-137
An Efficient RF Energy Harvester with Tuned Matching Circuit
Sachin Agrawal; Sunil Pandey; Jawar Singh; P. N. Kondekar
138-145
A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits
Surabhi Singh; Brajesh K. Kaushik; Sudeb Dasgupta
146-152
Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET
Jose Joseph; Rajendra Patrikar
153-159
Chapters/HeadingsAuthor(s)PagesInfo
Showing 1 to 20 of 46 entries
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