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Home > Embedded Computer Systems: Architectures, Modeling, and Simulation: 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings > Real-Time Stereo Vision on a Reconfigurable System
Embedded Computer Systems: Architectures, Modeling, and Simulation: 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings |
Timo D. Hämäläinen; Andy D. Pimentel; Jarmo Takala; Stamatis Vassiliadis
Springer Berlin Heidelberg
Embedded Computer Systems: Architectures, Modeling, and Simulation: 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings
Real-Time Stereo Vision on a Reconfigurable System
Authors

SungHwan Lee; Jongsu Yi; JunSeong Kim

ARI Id

1674219957766_4331195

Access

Not Available Free

Pages

299-307

DOI

10.1007/11512622_32

Chapter URL

https://rd.springer.com/chapter/10.1007/11512622_32

Table of Contents of Book
Showing 1 to 20 of 51 entries
Chapters/HeadingsAuthor(s)PagesInfo
Front Matter
Platform Thinking in Embedded Systems
Bob Iannucci
1-1
Interprocedural Optimization for Dynamic Hardware Configurations
Elena Moscu Panainte; Koen Bertels; Stamatis Vassiliadis
2-11
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques
M. Glesner; H. Hinkelmann; T. Hollstein; L. S. Indrusiak; T. Murgan; A. M. Obeid et al.
12-21
Reconfigurable Multiple Operation Array
Humberto Calderon; Stamatis Vassiliadis
22-31
RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration
Guillermo Payá Vayá; Javier Martín Langerwerf; Peter Pirsch
32-40
Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping
Ricardo Ferreira; João M. P. Cardoso; Andre Toledo; Horácio C. Neto
41-50
Automatic FIR Filter Generation for FPGAs
Holger Ruckdeschel; Hritam Dutta; Frank Hannig; Jürgen Teich
51-61
Two-Dimensional Fast Cosine Transform for Vector-STA Architectures
J. P. Robelly; A. Lehmann; G. Fettweis
62-71
Configurable Computing for High-Security/High-Performance Ambient Systems
Guy Gogniat; Wayne Burleson; Lilian Bossuet
72-81
FPL-3E: Towards Language Support for Reconfigurable Packet Processing
Mihai Lucian Cristea; Claudiu Zissulescu; Ed Deprettere; Herbert Bos
82-92
Flux Caches: What Are They and Are They Useful?
Georgi N. Gaydadjiev; Stamatis Vassiliadis
93-102
First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption
Cheol Hong Kim; Sunghoon Shim; Jong Wook Kwak; Sung Woo Chung; Chu Shik Jhon
103-111
A Novel JAVA Processor for Embedded Devices
Yiyu Tan; Chihang Yau; Kaiman Lo; Paklun Mok; Anthony S. Fong
112-121
Formal Specification of a Protocol Processor
Tomi Westerlund; Juha Plosila
122-131
Tuning a Protocol Processor Architecture Towards DSP Operations
Jani Paakkulainen; Seppo Virtanen; Jouni Isoaho
132-141
Observations on Power-Efficiency Trends in Mobile Communication Devices
Olli Silvén; Kari Jyrkkä
142-151
CORDIC-Augmented Sandbridge Processor for Channel Equalization
Mihai Sima; John Glossner; Daniel Iancu; Hua Ye; Andrei Iancu; A. Joseph Hoane
152-161
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic
Sunghoon Shim; Jong Wook Kwak; Cheol Hong Kim; Sung Tae Jhang; Chu Shik Jhon
162-171
Exploiting Intra-function Correlation with the Global History Stack
Fei Gao; Suleyman Sair
172-181
Chapters/HeadingsAuthor(s)PagesInfo
Showing 1 to 20 of 51 entries
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