"ASIC Design and Synthesis: RTL Design Using Verilog"

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Book	Author(s)	Year	Publisher
ASIC Design and Synthesis: RTL Design Using Verilog	Vaibbhav Taraate	1st ed. 2021	Springer Nature Singapore
Digital Logic Design Using Verilog: Coding and RTL Synthesis	Vaibbhav Taraate	1st ed. 2016	Springer India
Digital Logic Design Using Verilog: Coding and RTL Synthesis	Vaibbhav Taraate	2nd ed. 2022	Springer Nature Singapore
Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog	Vaibbhav Taraate	1st ed. 2019	Springer Nature Singapore
RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design	Stuart Sutherland	2017	Sutherland HDL, Inc.
Digital design,with RTL design,VHDL,and Verilog	Frank Vahid	2010	John Wiley
Logic Synthesis and SOC Prototyping: RTL Design using VHDL	Vaibbhav Taraate	1st ed. 2020	Springer Nature Singapore
Verilog Digital Design Synthesis	Samir Palnitkar	1996	SunSoft Press
Digital Design and Synthesis With Verilog Hdl.	Eli Sternheim	January 1993	Automata Pub Co
Advanced digital logic design: using Verilog, state machines, and synthesis for FPGAs /	Lee, Sunggu.	[2006], ©2006.	Thomson,
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®	Himanshu Bhathagar	1999	Springer US
PLD Based Design with VHDL: RTL Design, Synthesis and Implementation	Vaibbhav Taraate	1st ed. 2017	Springer Nature Singapore
Introduction to Logic Synthesis using Verilog HDL	Robert B. Reese; Mitchell A. Thornton		Springer International Publishing
High Performance ASIC Design: Using Synthesizable Domino Logic in an ASIC Flow	Razak Hossain	2008-08	Cambridge University Press
Digital Integrated Circuit Design Using Verilog and Systemverilog	Ronald W. Mehler	2015	Newnes
FSM-Based Digital Design using Verilog HDL	Peter Minns BSc(H), PhD, CEng, MIET,	2008	John Wiley & Sons
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime®	Himanshu Bhatnagar	2nd ed. 2002	Springer US
Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis	Mohamed S. Ben Romdhane; Vijay K. Madisetti; John W. Hines	1996	Springer US
Digital Computer Arithmetic Datapath Design Using Verilog HDL	James E. Stine	2004	Springer US
Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog	Lionel Bening; Harry D. Foster	2000	Springer US
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Showing 1 to 20 of 100 entries

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Chapter	Author(s)	Book	Book Authors	Year	Publisher
ASIC RTL Synthesis	Vaibbhav Taraate	Digital Logic Design Using Verilog: Coding and RTL Synthesis	Vaibbhav Taraate	1st ed. 2016	Springer India
3. RTL design with Verilog		Embedded core design with FPGAs /	Navabi, Zainalabedin.	2007.	McGraw-Hill,
Complex Designs Using Verilog RTL	Vaibbhav Taraate	Digital Logic Design Using Verilog: Coding and RTL Synthesis	Vaibbhav Taraate	1st ed. 2016	Springer India
Design Synthesis and Optimization Using RTL Tweaks	Vaibbhav Taraate	ASIC Design and Synthesis: RTL Design Using Verilog	Vaibbhav Taraate	1st ed. 2021	Springer Nature Singapore
ASIC Synthesis and Design Constraints	Vaibbhav Taraate	Logic Synthesis and SOC Prototyping: RTL Design using VHDL	Vaibbhav Taraate	1st ed. 2020	Springer Nature Singapore
RTL Design and Synthesis Guidelines	Vaibbhav Taraate	SystemVerilog for Hardware Description: RTL Design and Verification	Vaibbhav Taraate	1st ed. 2020	Springer Nature Singapore
RTL synthesis		Digital system design with VHDL	Zwoliński, Mark	2004;2010	Pearson; Prentice-Hall
RTL Synthesis		FPGA Design Automation (Foundations and Trends in Electronic Design Automation)	Deming Chen, Jason Cong, Peichan Pan	2006	Now Publishers Inc
Verilog synthesis		Digital VLSI chip design with Cadence and Synopsys CAD tools /	Brunvand, Erik.	c2010.	Addison-Wesley,
Hardware Design Using Verilog	Daniel Page	A Practical Introduction to Computer Architecture	Daniel Page	2009	Springer London
Verilog at the RTL Level	James E. Stine	Digital Computer Arithmetic Datapath Design Using Verilog HDL	James E. Stine	2004	Springer US
1851 Design process from RTL to ASIC or FPGA		CyBok: The Cyber Security Body of Knowledge	Awais Rashid; Howard Chivers; George Danezis; Emil Lupu; Andrew Martin	2019	National Cyber Security Centre
ASIC Design	Cesare Buffa	MEMS Lorentz Force Magnetometers: From Specifications to Product	Cesare Buffa	1st ed. 2018	Springer International Publishing
ASIC Design	Vikram Arkalgud Chandrasetty	VLSI Design: A Practical Guide for FPGA and ASIC Implementations	Vikram Arkalgud Chandrasetty	2011	Springer New York
ASIC Design	Wai-Kai Chen	Memory, Microprocessor, and ASIC	Wai-Kai Chen	2003	Routledge
ASIC Design	Vaibbhav Taraate	Digital Logic Design Using Verilog: Coding and RTL Synthesis	Vaibbhav Taraate	2nd ed. 2022	Springer Nature Singapore
Section 2: Introduction to Verilog RTL Design, Simulation, and Implementation		FPGA Programming for Beginners	Frank Bruno	2021	Packt Publishing
ASIC Design Using Silicon 1076	Robert A. Cottrell	VHDL for Simulation, Synthesis and Formal Proofs of Hardware	Jean Mermet	1992	Springer US
RTL Design	Philip Simpson	FPGA Design: Best Practices for Team-based Design	Philip Simpson	2010	Springer New York
RTL Design		Verilog: Frequently Asked Questions: Language, Applications and Extensions	Shivakumar S. Chonnad; Needamangalam B. Balachander	2004	Springer New York
Chapter	Author(s)	Book	Book Authors	Year	Publisher

Showing 1 to 20 of 100 entries

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