"Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms"

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Book	Author(s)	Year	Publisher
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms	Tim Kogel; Rainer Leupers; Heinrich Meyr	2006	Springer Netherlands
Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms	Andreas Wieferink; Heinrich Meyr; Rainer Leupers	2008	Springer Netherlands
Multi-Processor System-on-Chip 1 - Architectures	Liliana Andrade; Frédéric Rousseau	2021	John Wiley & Sons
Multi-Processor System-on-Chip 2 - Applications	Liliana Andrade; Frédéric Rousseau	2021	John Wiley & Sons
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip	Zheng Wang; Anupam Chattopadhyay	1st ed. 2018	Springer Nature Singapore
Processor and System-on-Chip Simulation	Rainer Leupers; Olivier Temam	2010	Springer US
Network-on-Chip: The Next Generation of System-on-Chip Integration	Santanu Kundu; Santanu Chattopadhyay	2015	Routledge
Modeling Multi-Level Systems	Octavian Iordache (auth.)	2011	Springer-Verlag Berlin Heidelberg
Modeling Multi-Level Systems	Octavian Iordache	2011	Springer Berlin Heidelberg
Multi-Stakeholder Platforms for Integrated Water Management	Jeroen Warner	2007	Routledge
Chip-level modeling with VHDL	James R. Armstrong	1989	Prentice Hall
System-Level Modeling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures	Gakgan Erbas	2006	Amsterdam University Press
Network and Multi-level Marketing	Allan Carmichael	September 1995	Concept (England)
Electronic System-Level HW/SW Co-Design of Heterogeneous Multi-Processor Embedded Systems	Luigi Pomante	2016	River Publishers
Heat management in integrated circuits: on-chip and system-level monitoring and cooling	Ogrenci-Memik, Seda	2015	The Institution of Engineering and Technology
System Level Design of Reconfigurable Systems-on-Chip	Nikolaos Voros; Konstantinos Masselos	2005	Springer US
Processor Design: System-On-Chip Computing for ASICs and FPGAs	Jari Nurmi	2007	Springer Netherlands
Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures	Umit Y. Ogras; Radu Marculescu	2013	Springer Netherlands
Integrated Optics: Modeling, Material Platforms and Fabrication Techniques	Giancarlo C. Righini, Maurizio Ferrari	2021	Institution of Engineering & Technology
System-level Modeling of MEMS	Gabriele Schrag	2013	John Wiley & Sons
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Chapter	Author(s)	Book	Book Authors	Year	Publisher
Network-on-Chip (NoC): The Technology that Enabled Multi-processor Systems-on-Chip (MPSoCs)	K. Charles Janac	Multi-Processor System-on-Chip 1 - Architectures	Liliana Andrade; Frédéric Rousseau	2021	John Wiley & Sons
Network-on-Chip Modeling for System-Level Multiprocessor Simulation	J. Madsen, S. Mahadevan, K. Virk and M. Gonzalez	RTSS 2003: 24th IEEE International Real-Time Systems Symposium: 3-5 December, 2003, Cancun, Mexico /	Workshop on Principles of Advanced and Distributed Simulation 20 2006 Singapur Verfasser \| Institute of Electrical and Electronics Engineers (New York, N.Y.) \| IEEE Computer Society \| IEEE Computer Society. \| Euromicro \| IEEE Computer Society. \| IEEE Computer Society.	[2003], ©2003.	IEEE Computer Society,
DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip	Philipp Wagner; Thomas Wild; Andreas Herkersdorf	Architecture of Computing Systems -- ARCS 2016: 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings	Frank Hannig; João M.P. Cardoso; Thilo Pionteck; Dietmar Fey; Wolfgang Schröder-Preikschat; Jürgen Teich	1st ed. 2016	Springer International Publishing
System-Level Design of Network-on-Chip Architectures	Karam S. Chatha; Krishnan Srinivasan	Designing Embedded Processors: A Low Power Perspective	Jörg Henkel; Sri Parameswaran	2007	Springer Netherlands
On-chip Network Modeling Infrastructure		On-Chip Networks: Second Edition	Natalie Enright Jerger, Tushar Krishna, Li-Shiuan Peh	2017	Morgan & Claypool Publishers
On-chip processor traffic modeling for networks-on-chip design	Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset	Networks-on-chips: theory and practice /	Gebali, Fayez.; Elmiligi, Haytham.; El-Kharashi, Mohamed Watheq.	2009.	Taylor & Francis,
A Parallel Genetic Algorithm on a Multi-Processor System-on-Chip	Rubem Euzébio Ferreira; Luiza de Macedo Mourelle; Nadia Nedjah	Trends in Applied Intelligent Systems: 23rd International Conference on Industrial Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2010, Cordoba, Spain, June 1-4, 2010, Proceedings, Part II	Nicolás García-Pedrajas; Francisco Herrera; Colin Fyfe; José Manuel Benítez Sánchez; Moonis Ali	2010	Springer Berlin Heidelberg
Multi-Processor System-on-Chip Prototyping Using Dynamic Binary Translation	Frédéric Pétrot; Luc Michel; Clément Deschamps	Handbook of Hardware/Software Codesign	Soonhoi Ha; Jürgen Teich	0th ed. 2020	Springer Netherlands
System Level Power Modeling and Simulation of High-End Industrial Network-On-Chip	Andrea Bona; Vittorio Zaccaria; Roberto Zafalon	Ultra Low-Power Electronics and Design	Enrico Macii	2004	Springer US
A Consideration of Processor Utilization on Multi-Processor System	Koichi Kashiwagi; Yoshinobu Higami; Shin-Ya Kobayashi	Advances in Information Processing and Protection	Jerzy Pejas; Khalid Saeed	2007	Springer US
Modeling of On-Chip Power Distribution Network	Chulsoon Hwang; Jingook Kim; Jun Fan; Joungho Kim; James L. Drewniak	Noise Coupling in System-on-Chip	Thomas Noulis	2017	Routledge
Multi-Level Modeling		The VLSI handbook	Wai-Kai Chen	2000	CRC Press; IEEE Press
processor chip	Martin H. Weik	Computer Science and Communications Dictionary	Martin Weik	2001	Springer US
High-level modeling and exploration of a powerline communication network based on System-on-Chip	Marcos Martinez; David Ferruz; Hector Posadas; Eugenio Villar	Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach	Cristina Silvano; William Fornaciari; Eugenio Villar	2011	Springer New York
An Architecture of On-Chip-Memory Multi-Threading Processor	T. Matsuzaki, H. Tomiyasu and M. Amamiya.	Innovative architecture for future generation high-performance processors and systems: 18-19 January, 2001, Maui, Hawaii /	Veidenbaum, Alex.; Joe, Kazuki.	[2001], ©2001.	IEEE Computer Society,
A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication	Vincenzo Rana; David Atienza; Marco Domenico Santambrogio; Donatella Sciuto; Giovanni De Micheli	VLSI-SoC: Design Methodologies for SoC and SiP: 16th IFIP WG 10. 5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2008, Rhodes Island, Greece, October 13-15, 2008, Revised Selected Papers	Christian Piguet; Ricardo Reis; Dimitrios Soudris	2010	Springer Berlin Heidelberg
Multi-Level Network-on-Chip Design Based on Embedded Unified Rendering GPU	Ye Li; Huiming Du; Libo Chang; Haowen Wang	Advances in Natural Computation, Fuzzy Systems and Knowledge Discovery: Proceedings of the ICNC-FSKD 2021	Quan Xie; Liang Zhao; Kenli Li; Anupam Yadav; Lipo Wang	1st ed. 2022	Springer International Publishing
Two-Level Multi-Level Modeling	Ding-Geng (Din) Chen; Jenny K. Chen	Statistical Regression Modeling with R: Longitudinal and Multi-level Modeling	Ding-Geng (Din) Chen; Jenny K. Chen	1st ed. 2021	Springer International Publishing
Higher-Level Multi-Level Modeling	Ding-Geng (Din) Chen; Jenny K. Chen	Statistical Regression Modeling with R: Longitudinal and Multi-level Modeling	Ding-Geng (Din) Chen; Jenny K. Chen	1st ed. 2021	Springer International Publishing
Integrated System Modeling	Peter J. Ashenden; Gregory D. Peterson; Darrell A. Teegarden	The System Designer's Guide to VHDL-AMS	Peter J. Ashenden; Gregory D. Peterson and Darrell A. Teegarden	2003	Morgan Kaufmann
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Showing 1 to 20 of 100 entries

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