"Logic Decomposition with Technology Mapping for Area and Delay Minimization in FPGA Design."

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Book	Author(s)	Year	Publisher
Logic Synthesis for FPGA-Based Control Units: Structural Decomposition in Logic Design	Alexander Barkalov; Larysa Titarenko; Kamil Mielcarek; Sławomir Chmielewski	1st ed. 2020	Springer International Publishing
Technology Mapping for LUT-Based FPGA	Marcin Kubica; Adam Opara; Dariusz Kania	1st ed. 2021	Springer International Publishing
Functional Decomposition with Applications to FPGA Synthesis	Christoph Scholl	2001	Springer US
Digital Logic: With an Introduction to Verilog and FPGA-Based Design	M. Rafiquzzaman, Steven A. McNinch	2019	Wiley
Logic Minimization Algorithms for VLSI Synthesis	Robert K. Brayton; Gary D. Hachtel; C. McMullen; Alberto L. Sangiovanni-Vincentelli	1984	Springer US
FPGA Design: Best Practices for Team-based Design	Philip Simpson (auth.)	2010	Springer-Verlag New York
FPGA Design: Best Practices for Team-based Design	Philip Simpson	2010	Springer New York
Real World FPGA Design with Verilog [With CDROM]	Coffman, Ken	1999	Prentice Hall
Logic Synthesis for FPGA-Based Finite State Machines	Alexander Barkalov; Larysa Titarenko; Malgorzata Kolopienczyk; Kamil Mielcarek; Grzegorz Bazydlo	1st ed. 2016	Springer International Publishing
FPGA-Design mit Verilog	Harald Flügel	2010	Oldenbourg Wissenschaftsverlag
FPGA-Based System Design	Wolf, Wayne	2004	Prentice Hall
Numerical conformal mapping: Domain decomposition and the mapping of quadrilaterals	Papamichael N., Stylianopoulos N.	2010	WS
FPGA Design Automation (Foundations and Trends in Electronic Design Automation)	Deming Chen, Jason Cong, Peichan Pan	2006	Now Publishers Inc
Design of FPGA-Based Computing Systems with OpenCL	Hasitha Muthumala Waidyasooriya; Masanori Hariyama; Kunio Uchiyama	1st ed. 2018	Springer International Publishing
Visible area mapping	Charles A. Abell	1936	Appalachian Forest Experiment Station
Handbook of FPGA Design Security	Ted Huffmire; Cynthia Irvine; Thuy D. Nguyen; Timothy Levin; Ryan Kastner; Timothy Sherwood	2010	Springer Netherlands
RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design	Stuart Sutherland	2017	Sutherland HDL, Inc.
FPGA Design: Best Practices for Team-based Reuse	Philip Andrew Simpson	2nd ed. 2015	Springer International Publishing
Logic and logic design	B. Girling	1973	International Textbook Co.
Causal Mapping for Research in Information Technology	V. K. Nakayama	January 2005	IGI Global
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Chapter	Author(s)	Book	Book Authors	Year	Publisher
FPGA technology mapping for power minimization	Amir H. Farrahi; Majid Sarrafzadeh	Field-Programmable Logic: Architectures, Synthesis and Applications: 4th International Workshop on Field-Programmable Logic and Applications, FPL' 94, Prague, Czech Republic, September 7 - 9, 1994. Proceedings	Reiner W. Hartenstein; Michal Z. Servit	1994	Springer Berlin Heidelberg
821 Logic Minimization & Technology Mapping		Low-Power Digital VLSI Design	Abdellatif Bellaouar, Mohamed Elmasry	1995	Springer
Logic Decomposition during Technology Mapping	Eric Lehman; Yosinori Watanabe; Joel Grodstein; Heather Harkness	The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design	Andreas Kuehlmann	2003	Springer US
LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth	H. Li, W.-K. Mak and S. Katkoori	IEEE Computer Society Workshop on VLSI 2000[sic]: proceedings: 19-20 April, 2001, Orlando, Florida /	Smailagic, Asim,; De Man, H.	[2001], ©2001.	IEEE Computer Society,
FPGA Technology Mapping	Jason Cong; Yuzheng Ding	Encyclopedia of Algorithms	Ming-Yang Kao	2nd ed. 2016	Springer New York
FPGA Technology Mapping	Jason Cong; Yuzheng Ding	Encyclopedia of Algorithms	Ming-Yang Kao	0th ed. 2020	Springer Berlin Heidelberg
5. FPGA Technology Mapping		Genetic algorithms for VLSI design, layout & test automation /	Mazumder, Pinaki.; Rudnick, Elizabeth M.	[1999], ©1999.	Prentice Hall PTR,
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits	Bertrand Folco; Vivian Brégier; Laurent Fesquet; Marc Renaudin	VLSI-SoC: From Systems to Silicon: IFIP TC10/ WG 10. 5 Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2005), October 17-19, 2005, Perth, Australia	Ricardo Reis; Adam Osseiran; Hans-Joerg Pfleiderer	2007	Springer US
Constraint Based Technology Mapping in Logic Design	S. Fujita; M. Iwamoto; M. Watanabe	Artificial Intelligence in Design ’94	John S. Gero; Fay Sudweeks	1994	Springer Netherlands
Approximate Logic Synthesis for FPGA by Decomposition	Zhiyuan Xiang; Niyiqiu Liu; Yue Yao; Fan Yang; Cheng Zhuo; Weikang Qian	Approximate Computing	Weiqiang Liu; Fabrizio Lombardi	1st ed. 2022	Springer International Publishing
FPGA Technology Mapping, Placement, and Routing	Kia Bazargan	Handbook of Algorithms for Physical Design Automation	Charles J. Alpert; Dinesh P. Mehta; Sachin S. Sapatnekar	2009	Routledge
Parallel Performance Directed Technology Mapping for FPGA	Laurent Lemarchand	SSMSD 99: 1999 Southwest Symposium on Mixed-Signal Design: April 11-13, 1999, Tucson, Arizona, U. S. A.	Carothers, Jo Dale.	[1999], ©1999.	IEEE,
An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs	Jason Cong; Yuzheng Ding	The Best of ICCAD: 20 Years of Excellence in Computer-Aided Design	Andreas Kuehlmann	2003	Springer US
FPGA Architecture Design and Toolset for Logic Implementation	K. Tatas; K. Siozios; N. Vasiliadis; D. J. Soudris; S. Nikolaidis; S. Siskos et al.	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings	Jorge Juan Chico; Enrico Macii	2003	Springer Berlin Heidelberg
UML Support for Statecharts-Based Digital Logic Controller Design in FPGA Technology	Grzegorz Łabiak	Design of Reconfigurable Logic Controllers	Andrei Karatkevich; Arkadiusz Bukowiec; Michał Doligalski; Jacek Tkacz	1st ed. 2016	Springer International Publishing
Drawing Your FPGA Logic Design		Practical Electronics for Inventors	Paul Scherz, Simon Monk	2016	McGraw-Hill
FPGA Design by Generalized Functional Decomposition	Tsutomu Sasao	Logic Synthesis and Optimization	Tsutomu Sasao	1993	Springer US
Delay Insensitive Logic for RSFQ Superconductor Technology	P. Patra, S. Polonsky and D. S. Fussell	Proceedings, Third International Symposium on Advanced Research in Asynchronous Circuits and Systems: April 7-10, 1997, Eindhoven, The Netherlands /	International Symposium on Advanced Research in Asynchronous Circuits	[1997], ©1997.	IEEE Computer Society Press,
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation	Joseph Zambreno; David Nguyen; Alok Choudhary	Field Programmable Logic and Application: 14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings	Jürgen Becker; Marco Platzner; Serge Vernalde	2004	Springer Berlin Heidelberg
Logic Minimization		Real World FPGA Design with Verilog [With CDROM]	Coffman, Ken	1999	Prentice Hall
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