"Simulating Multiprocessor Architectures for Compiled Graph-Reduction"

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Book	Author(s)	Year	Publisher
An Architecture for Combinator Graph Reduction	Philip John Koopman	1990	Academic Press
Modeling and Simulating Software Architectures: The Palladio Approach	Ralf H. Reussner; Steffen Becker; Jens Happe; Anne Koziolek; Heiko Koziolek	2016	MIT Press
Combinators and Graph Reduction (in Scheme)	Rhys Price Jones, Fritz Ruehr, Richard Salter	1996	www.cs.oberlin.edu
Interactive graph reduction and analysis program	James Winton Thomas	1970	Naval Postgraduate School
System-Level Modeling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures	Gakgan Erbas	2006	Amsterdam University Press
Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach	Cristina Silvano; William Fornaciari; Eugenio Villar	2011	Springer New York
A multiprocessor for simulation applications.	Edward Willmore Davis	1972	Dept. of Computer Science, University of Illinois at Urbana-Champaign
Multiprocessor performance	E. Gelenbe	1989	Wiley
Multiprocessor Scheduling for Real-Time Systems	Sanjoy Baruah; Marko Bertogna; Giorgio Buttazzo	2015	Springer International Publishing
Multiprocessor Methods for Computer Graphics Rendering	Scott Whitman	1992	Routledge
Architectures for intelligence	Carnegie Symposium on Cognition (22nd 1988 Carnegie-Mellon University)	1991	L. Erlbaum Associates;Psychology Press
Pipelined Multiprocessor System-on-Chip for Multimedia	Haris Javaid; Sri Parameswaran	2014	Springer International Publishing
Queuing delaymodeling for multistage interconnection multiprocessor networks.	Paul G. Spirakis	1984	Courant Institute of Mathematical Sciences, New York University
Simulating terrorism	Stephen Sloan	1981	University of Oklahoma Press
Simulating navigation for spatial knowledge acquisition	Sarah E. Goldin	1981	Rand
Domain architectures: models and architectures for UML applications	Daniel J. Duffy	2004	John Wiley & Sons
Inequalities for Graph Eigenvalues	Zoran Stanić	2015-07	Cambridge University Press
Multiprocessor Systems-on-Chips	Ahmed Amine Jerraya and Wayne Wolf	2005	Morgan Kaufmann
A multiprocessor operating system	Joseph, M.	1984	Prentice/Hall International
Architectures for Enterprise Integration	Peter Bernus; Laszlo Nemes; Theodore J. Williams	1996	Springer US
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Chapter	Author(s)	Book	Book Authors	Year	Publisher
Simulating Multiprocessor Architectures for Compiled Graph-Reduction	J. M. Deschner	Functional Programming: Proceedings of the 1989 Glasgow Workshop 21–23 August 1989, Fraserburgh, Scotland	Kei Davis; John Hughes	1990	Springer London
Multiprocessor Architectures	Wayne Wolf	High-Performance Embedded Computing	Wayne Wolf	2007	Morgan Kaufmann
Multiprocessor Architectures	Marilyn Wolf	High-Performance Embedded Computing (Second Edition)	Marilyn Wolf	2014	Morgan Kaufmann
Multiprocessor Architectures		Handbook of Real-Time Fast Fourier Transforms: Algorithms to Product Testing	Winthrop W. Smith	1995	Wiley-IEEE Press
MaRS, a combinator graph reduction multiprocessor	A. Contessa; E. Cousin; C. Coustet; M. Cubero-Castan; G. Durrieu; B. Lecussan et al.	PARLE ' 89 - Parallel Architectures and Languages Europe: Volume I: Parallel Architectures, Eindhoven, The Netherlands, June 12-16, 1989; Proceedings	Eddy Odijk; Martin Rem; Jean-Claude Syre	1989	Springer Berlin Heidelberg
54 Multiprocessor Architectures		High-Performance Embedded Computing - Architectures, Applications, And Methodologies	Wayne Wolf	2006	Morgan Kaufmann
Chip MultiProcessor architectures		Optimizations and Cost Models for multi-core architectures: an approach based on parallel paradigms	Daniele Buono	2014	Università di Pisa
111 Multiprocessor Architectures		Control Software For Mechanical Systems Object Oriented Design In A Real Time World	D.M. Auslander, J.R. Ridgely, J.D. Ringgenberg	2002	Prentice Hall
Compiled Graph Reduction on a Processor Network	Martin Raber; Thomas Remmel; Erwin Hoffmann; Dieter Maurer; Fritz Müller; Hans-Georg Oberhauser et al.	Architektur und Betrieb von Rechensystemen: 10. GI/ITG-Fachtagung Paderborn, 9. –11. März 1988 Proceedings	Uwe Kastens; Franz Josef Rammig	1988	Springer Berlin Heidelberg
Alfalfa: Distributed graph reduction on a hypercube multiprocessor	Benjamin Goldberg; Paul Hudak	Graph Reduction: Proceedings of a Workshop Santa Fe, New Mexico, USA, September 29 - October 1, 1986	Joseph H. Fasel; Robert M. Keller	1987	Springer Berlin Heidelberg
Challenges in Multiprocessor Architectures	John Hennessy	Opportunities and Constraints of Parallel Computing	Jorge L.C. Sanz	1989	Springer New York
84 CHIP MULTIPROCESSOR ARCHITECTURES		Parallel Computer Organization and Design	Michel Dubois, Murali Annavaram, Per Stenström	2012	Cambridge University Press
CPU Packing for Multiprocessor Power Reduction	Soraya Ghiasi; Wes Felter	Power-Aware Computer Systems: Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003, Revised Papers	Babak Falsafi; T. N. Vijaykumar	2005	Springer Berlin Heidelberg
7 Integrated Photonics for Chip-Multiprocessor Architectures		Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges	Mahdi Nikdast; Gabriela Nicolescu; Sébastien Le Beux; Jiang Xu	2017	River Publishers
Graph-reduction		Compiling functional languages	Antoni Diller	1988	Wiley
833 UMA Symmetric Multiprocessor Architectures		Structured computer organization	Tanenbaum, Andrew Stuart; Austin, Todd; Chandavarkar, B.R	2012;2013	Pearson Education
94 PARALLEL AND MULTIPROCESSOR ARCHITECTURES		The Essentials of Computer Organization and Architecture	Linda Null, Julia Lobur	2003	Jones and Bartlett Publishers
833 UMA Symmetric Multiprocessor Architectures		Structured Computer Organization: United States Edition	Andrew S. Tanenbaum	2005	Pearson
833 UMA Symmetric Multiprocessor Architectures		Structured computer organization	Tanenbaum, Andrew S; Austin, Todd	2012;2017	Pearson; Langara College
833 UMA Symmetric Multiprocessor Architectures		Structured Computer Organization, 5th Edition	Andrew S. Tanenbaum	2005	Prentice Hall
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